library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity immExt is
  
  port (
    imm    : in  std_logic_vector(15 downto 0);
    sign   : in  std_logic;
    extend : out std_logic_vector(31 downto 0);
    upper  : out std_logic_vector(31 downto 0));

end immExt;

architecture arch of immExt is

begin  -- arch

  upper(31 downto 16)  <= imm;
  upper(15 downto 0)   <= (others => '0');
  extend(15 downto 0)  <= imm;
  extend(31 downto 16) <= (others => (sign and  imm(15)));

end arch;
